Recently in various recording and reproduction apparatuses and communication apparatuses, input data has been encoded to reduce the data error rate of a digital transfer signal.
FIG. 1 is a block diagram of a digital signal processing circuit in a general recording and reproduction apparatus.
An encoding section 1 encodes input data at a ratio of m:n, where m indicates a data bit length before encoding and n indicates a data bit length after encoding. A D/A converter 2 converts an input recording code from a digital signal to an analog signal, that is, to a recording rectangular wave. A recording and reproduction section 3 includes, for example, a magnetic head, an optical pickup, and a control circuit for controlling the driving thereof, and records the recording wave input from the D/A converter 2 in a recording medium not shown.
The recording and reproduction section 3 reproduces a signal recorded in the recording medium, and outputs an analog reproduced wave to an analog equalizer 4. The analog equalizer 4 equalizes the reproduced wave input from the recording and reproduction section 3 so as to have a predetermined target equalization characteristic.
An A/D converter 5 includes a PLL (phase locked loop) circuit. It may be a hybrid digital PLL in which only phase error detection is performed by a digital section, or a full digital PLL in which both phase error detection and signal synchronization are performed by a digital section.
When equalization applied by the analog equalizer 4 is insufficient, a digital equalizer may further be provided between the A/D converter 5 and a code detection section 6. In this case, instead of the analog equalizer 4, a low-pass filter may be provided.
The code detection section 6 is formed recently of a maximum-likelihood detector generally, and converts an input digital reproduced signal, that is, an equalized signal to a code. In other words, the code detection section 6 detects a code. A decoding section 7 decodes an input detected code at a ratio of n:m to generate output data and output it.
In FIG. 1, as a code used in the encoding section 1, various codes have been made practical. These codes are basically divided into convoluted codes and block codes. Consecutive encoding is performed for convoluted codes whereas an information string is partitioned and independent codes are generated for block codes. In recording and reproduction apparatuses, block codes are generally used in many cases, which provide a relatively successful characteristic even at a large encoding rate.
For example, an 8/9 conversion code and a 16/17 conversion code have been made practical for recording and reproduction apparatuses which use a hard disk, and an 8/10 conversion code and a 16/20 conversion code have been made practical for 3.8-mm and 8-mm tape streamer magnetic recording and reproduction apparatuses. For these block codes which have been made practical, one type of conversion rule is repeatedly applied to all blocks of input data to execute encoding and decoding.
Contrarily, an idea has been proposed in which two different types of block codes are alternately and repeatedly applied and the encoded blocks thereof are concatenated to configure a trellis code having a high encoding rate and a reduced data error rate. The trellis code in which two different types of block codes are alternately concatenated is hereinafter called an “alternate-conversion trellis code”.
For example, a paper, L. Fredricson, et al., “Trellis coding in the Venus Read/Write Channel,” IEEE trans. on Magn., vol. 33, No. 5, pp. 2743-2745, September, 1997, discloses an alternate-conversion trellis code which can configure a 12/15 conversion trellis code having an encoding rate of 0.8. Japanese Unexamined Patent Application Publication No. Hei-11-186917, and another paper, M. Noda, “High-Rate Matched Spectral Null code,” IEEE Trans. on Magn., vol. 34, No. 4, pp. 1946-1948, July, 1998, disclose the structure of a code having a higher encoding rate. With the use of this technology, a 24/27 conversion trellis code having an encoding rate of about 0.889, for example, can be configured.
It has been pointed out in these alternate-conversion trellis codes that, when the number of codeword bits is odd, one of two different types of block codes can be converted in a simple circuit to obtain the other block code. Therefore, it is estimated that a circuit for executing substantial encoding and decoding with an alternate-conversion trellis code can be implemented at almost the same size as that of a circuit used with one type of block code.
In the alternate-conversion trellis code disclosed in the paper, L. Fredricson, et al., “Trellis coding in the Venus Read/Write Channel,” IEEE trans. on Magn., vol. 33, No. 5, pp. 2743-2745, September, 1997, NRZ (non return to zero) modulation is a prerequisite, and by reversing the order of one block code of two different types of block codes and by inverting all codewords so as to satisfy a transition state, the other block code can be obtained.
In the alternate-conversion trellis code disclosed in the another paper, M. Noda, “High-Rate Matched Spectral Null code,” IEEE Trans. on Magn., vol. 34, No. 4, pp. 1946-1948, July, 1998, NRZI (non return to zero inverted (non return to zero on one)) modulation is a prerequisite, and by reversing the order of one block code of two different types of block codes, by shifting by one bit, and by inverting, if necessary, only the top code so as to satisfy a transition state, the other block code can be obtained.
In one of the problems of conventional technologies related to encoding and decoding, since code conversion having a long bit constraint length generates a large number of converted codewords, if conversion is performed directly, a circuit for executing encoding and decoding becomes complicated exponentially corresponding to the bit constraint length.
As one of specific countermeasures to solve this problem, for example, there is a code division method, which substantially reduces a required number of converted codewords. When the code division method disclosed in a paper, a. Wldmer and P. Franaszec, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM J. Res. Develop., Vol. 27, No. 5, pp. 440-451, September, 1983, is used, an 8/10 conversion DC free code is code-divided into two independent 3/4 conversion code and 5/6 conversion code to reduce the required number of converted codewords from the eighth power of 2, that is, 256, to the sum of the third power of 2 and the fifth power of 2, that is, 40, which is a reduction of about 84 percent.
When the code division method disclosed in Japanese Unexamined Patent Application Publication No. Hei-11-215003 is used, a 16/18 conversion DC free code is code-divided into two independent 7/8 conversion code and 9/10 conversion code to reduce the required number of converted codewords from the 16th power of 2, that is, 65,536, to the sum of the seventh power of 2 and the ninth power of 2, that is, 640, which is a reduction of about 99 percent.
These code division methods have been discovered and applied by individually checking their converted codes. They cannot be applied to all codes.
For the alternate-conversion trellis codes described above, a combination of such code division methods is possible in some cases. Then, it is possible to much reduce the size of a circuit for executing encoding and decoding. According to M. Noda, “High-Rate Matched Spectral Null code,” IEEE Trans. on Magn., vol. 34, No. 4, pp. 1946-1948, July, 1998, for example, only one of two different block codes alternately used in 24/27 conversion trellis code is code-divided into two independent 12/13 conversion code and 12/14 conversion code to reduce the required number of converted codewords from the 24th power of 2, that is, 16,777,216 to the sum of the 12th power of 2 and the 12th power of 2, that is, 8,192, which is a reduction of about 99.95 percent.
As described above, two different types of block codes are used in the alternate-conversion trellis code disclosed in Japanese Unexamined Patent Application Publication No. Hei-11-186917, and the another paper, M. Noda, “High-Rate Matched Spectral Null code,” IEEE Trans. on Magn., vol. 34, No. 4, pp. 1946-1948, July, 1998, by reversing the order of one block code of the two different types of block codes, by shifting by one bit, and by inverting, if necessary, only the top code so as to satisfy a transition state, the other block code can be obtained.
To make such an alternate-conversion trellis code which uses NRZI modulation practical, however, it is necessary to determine whether the top code is to be inverted or not by determining whether a transition state is satisfied. A specific condition determination method has not yet been decided. In addition, a technology which implements processing for determining a condition to determine whether the top code is to be inverted or not, and, if necessary, for inverting the code, that is, a specific circuit structure which can be implemented, has not yet been clarified. Further, a method for decoding the converted top code to generate the original code has also not been decided.
Furthermore, similarly, to also make an alternate-conversion trellis code to which a code division method is applied practical, it is necessary to determine whether the top code is to be inverted or not by determining whether a transition state is satisfied, and the converted top code needs to be decoded to generate the original code. But a specific condition determination method therefore or a circuit structure therefor has not yet been clarified.